A semiconductor memory test apparatus inputs a test pattern signal to a memory device, and compares a response output signal from the memory device with an expected value pattern signal. Further, it detects a mismatch of a comparison result as a failure of the memory cell, and stores failure information (fail data) in a failure analysis memory. In the failure analysis memory, the same address space as that of the memory device is set, and failure information is stored at the same address as an address of a failure cell.
Meanwhile, in recent years, in a memory device such as an SDRAM (synchronous DRAM), an increase in data read/write speed is achieved by an operation in a burst mode. In the burst mode, when only a start address (first address) is given, subsequent addresses are sequentially automatically generated.
Therefore, in a test of the memory device which operates in the burst mode, only the start address is inputted to the memory device. On the contrary, not only the start address but also addresses which are automatically generated in the memory device must be inputted to the failure analysis memory. Thus, in a conventional semiconductor memory test apparatus, there are inputted the start address as well as addresses sequentially obtained by operating the start address in the burst period. As a result, the same address space as that of the memory device as a device under test can be set in the failure analysis memory.
An address generation operation in the conventional semiconductor memory test apparatus will now be described with reference to a timing chart of FIG. 4.
FIG. 4 shows an example of a timing of address generation when testing an SDRAM which has a plurality of banks, operates with respect to row addresses in a burst mode and has burst length of “2”.
(A) in FIG. 4 shows input timings of a command, an address and a bank address to a memory device under test (DUT). Furthermore, (B) in FIG. 4 shows generation timings of a row address (Row), a start column address (Col), an increment and a bank address in an address generator of a test pattern generator (ALPG). Moreover, (C) in FIG. 4 shows input timings of a row address (Row) and a column address (Col) as failure analysis addresses to a failure analysis memory (FM).
A description will now be given as to generation timings of addresses and the like in the test pattern generator indicated by (B) in FIG. 4, input timings of addresses and the like to the memory device indicated by (A) in FIG. 4, and input timings of addresses and the like to the failure analysis memory indicated by (C) in FIG. 4 in the mentioned order.
(1) Generation Timing in Test Pattern Generator
{circle around (1)} Row Address (X) and Bank Address (N)
As indicated by (B) in FIG. 4, the address generator continuously generates a bank address (RBK) and a row address (Row) after a clock cycle <1>. Here, as the bank address, “RBK (0)” specifying a 0th bank of the SDRAM is generated. Additionally, as the row address, “Row (0) 0” indicative of the 0th row of the 0th bank is generated.
{circle around (2)} Bank Address (B) and Start Column Address (Y)
Further, the address generator continuously generates a bank address (CBK) specifying a bank which stores a column address after a clock cycle <2>. Here, as the bank address, “CBK (0)” specifying the 0th bank is generated.
It is to be noted that the bank address (CBK) generated together with the start column address specifies the same bank (e.g., the 0th bank) as the bank specified by the bank address (RBK) generated together with the row address.
Furthermore, the address generator sequentially generates a start column address (Col) for each burst length in a period that the bank address “CBK (0)” is generated. Here, since the burst length is “2”, every other address value is generated in accordance with each two clock cycles.
That is, as the start column address, “Col (0) 0” indicative of the 0th column (first address) of the 0th bank is generated in the cycles <2> and <3>. Subsequently, “Col (0) 2” indicative of the second column as a next first address is generated in the cycles <4> and <5>. Then, “Col (0) 4” indicative of the fourth column is generated in the cycles <6> and <7>. In this manner, the start column addresses are thereafter sequentially generated.
{circle around (3)} Increment Value (Z)
Moreover, the generated start column address is incremented in accordance with a clock cycle. Therefore, a value (Z) to be incremented is repeatedly generated in accordance with each cycle period corresponding to the burst length.
That is, “0” is generated as the increment of the first cycle <2> in the cycles <2> and <3> in which the 0th column is generated as the start column address, and “1” is generated as the increment in the next cycle <3>. Then “0” and “1” are thereafter alternately generated as the increment for each cycle since the burst length is “2” in this example.
(2) Input Timing to Memory Device
The row address, the row bank address, the column address and the column bank address together with commands are multiplexed and inputted to the SDRAM. That is, in addresses generated in the address generator, only an address generated at the time of inputting a command is effective in the SDRAM.
In the example indicated by (A) in FIG. 4, the row address and the bank address are inputted to the SDRAM together with a command “ACT” in the cycle <1>. Here, as the bank address, a bank address “RBK (0)” specifying the 0th bank is inputted. Additionally, as the row address, “Row (0) 0” indicative of the 0th row of the 0th bank is inputted.
It is to be noted that the command “ACT” instructs activation of a target bank of the SDRAM, and also instructs input of the row address to that bank.
Subsequently, in the cycle <2>, the start column address and the bank address are inputted to the SDRAM together with a command “READ”. Here, as the bank address, a bank address “CBK (0)” specifying the 0th bank is inputted. Further, as the start column address, “Col (0)” indicative of the 0th column of the 0th bank is inputted.
This command “READ” instructs reading from a corresponding memory cell of the SDRAM. Therefore, in the cycle <2>, information in the memory cell at the 0th row (Row (0) 0) and the 0th column (Col (0) 0) of the 0th bank (BK (0)) is read.
It is to be noted that information is written in a corresponding memory cell when a command “WRITE” is inputted in place of the command “READ”.
The SDRAM has a burst function with respect to the column-addresses. That is, in the memory device, the start column address is automatically incremented for each clock cycle, and the column address is then sequentially generated.
Therefore, in the cycle <3>, the start column address is incremented in the memory address, and a column address “Col (0) 1” indicative of the first column is generated. Accordingly, in the cycle <3>in the burst operation, information of a next cell is outputted as a response output from the memory address even if the command “READ” or the column address is not inputted.
In this conventional example, since the burst length is “2”, the command “READ”, the next start column address and the bank address “CBK (0)” are thereafter inputted every other cycle. That is, the even-numbered start column addresses “Col (0) 2”, “Col (0) 4”, “Col (0) 6”, . . . are sequentially inputted in even-numbered cycles <4>, <6>, <8>, . . .
Therefore, in the odd-numbered cycles <3>, <5>, <7>, . . . , commands and the like are not inputted from the test pattern generator to the SDRAM at all.
(3) Input Timing to Failure Analysis Memory
{circle around (1)} Row Address (X) and Bank Address (N)
Therefore, in the example indicated by (C) in FIG. 4, after the cycle <1>, the bank address “RBK (0)” specifying the 0th bank and the row address “Row (0) 0” indicative of the 0th row of the 0th bank are continuously inputted. These bank address and row address are the same as those generated in the command generator.
(2) Column Address (Y+Z) and bank address (B) Furthermore, after the cycle. <2>, the bank address “CBK (0)” specifying the 0th bank is continuously inputted.
Then, in each cycle after the cycle <2>, a column address obtained by adding an increment value (Z) to the start column address (Y) generated in the address generator is inputted to the failure analysis memory. That is, in the cycles <2>, <3>, <4>, . . . , the column addresses “Col (0) 0”, “Col (0) 1”, “Col (0) 2”, . . . are sequentially inputted. As a result, the same address space as that in the SDRAM can be set in the failure analysis memory.
After the test with respect to each memory cell in the 0th bank is completed in this manner, each memory cell in the next first bank is tested. In case of testing the first bank, the test of the same timing as that of addresses and the like in the 0th bank is carried out except that an address specifying the first bank is determined as the bank address. Thereafter, the remaining banks are likewise sequentially tested in the same manner.
Meanwhile, in the memory device, a memory area is divided into a plurality of banks, and an inter-bank interleave operation to alternately perform reading/writing with respect to these banks may be performed. Carrying out the inter-bank interleave operation can increase an access speed to the memory.
When the memory device is operated in the inter-bank interleave mode, in the memory device, a row address is given in accordance with each bank in advance by the command “ACT”, and reading/writing of a cell is conducted corresponding to a column address of a specified bank together with the command “READ” or “WRITE”.
However, in the failure analysis memory, fail information is stored at an address corresponding to a row address and its bank of the memory device under test when a column address and its bank are specified. Therefore, in the failure analysis memory, when the column address and the bank of that column address are specified for the memory device under test, the same bank as that bank and a row address of that bank must be simultaneously specified. In the failure analysis memory, the same address space as that in the memory device under test must be set.
Therefore, in the conventional semiconductor memory test apparatus, the memory device having the burst function is hard to generate an address which is inputted to the failure analysis memory used to test the inter-bank interleave operation.
Accordingly, in view of the above-described problems, it is an object of the present invention to provide a semiconductor memory test apparatus and a failure analysis address generator by which a memory device having a burst function can readily generate an address which is inputted to a failure analysis memory used to test an inter-bank interleave operation.